Idp (Dai) Interrupt Service Routines For Dmas - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

IDP (DAI) Interrupt Service Routines for DMAs

The IDP can trigger either the high priority DAI core interrupt reflected
in the
DAI_IRPTL_H
reflected in the
ing
DAI_IRPTL_H
currently latched. The
rupts and the
DAI_IRPTL_L
When these registers are read, it clears the latched interrupt bits. This is a
destructive read.
The following steps describe how an IDP ISR should be handled.
1. When the DMA for a channel completes, an interrupt is generated
and program control jumps to the ISR.
2. The program should clear the
register (= 0).
3. The program should read the
to determine which DMA channels have completed.
To ensure that the DMA of a particular IDP channel is complete,
(all data is transferred into internal memory) wait until the
MAx_STAT
This is required if a high priority DMA (for example a SPORT
DMA) is occurring at the same time as the IDP DMA.
As each DMA channel completes, a corresponding bit in either the
DAI_IRPTL_L
(
IDP_DMAx_INT
Figure A-74 on page A-170
DAI_IRPTL_L
4. Reprogram the DMA registers for finished DMA channels.
ADSP-2126x SHARC Processor Hardware Reference
register or the low priority DAI core interrupt
register. The ISR must read the correspond-
DAI_IRPTL_L
or register to find all the interrupts
DAI_IRPTL_L
DAI_IRPTL_H
register reflects the low priority interrupts.
bit of that channel becomes zero in the
or
DAI_IRPTL_H
). Refer to Figure A-73 on page A-169
or
DAI_IRPTL_H
register reflects the high priority inter-
bit in the
IDP_DMA_EN
or
DAI_IRPTL_L DAI_IRPTL_H
registers for each DMA channel is set
for more information on the
registers.
Input Data Port
IDP_CTL
registers
IDP_D-
register.
DAI_STAT
and
11-23