Interrupt Servicing Sequence; Configuring Interrupts - Analog Devices adsp-2100 Manual

3 Program Control
3.4.1
When an interrupt request occurs, it is latched while the processor finishes
executing the current instruction. The interrupt request is then compared
with the interrupt mask register, IMASK, by the interrupt controller.
If the interrupt is not masked, the program sequencer pushes the current
value of the program counter (which contains the address of the next
instruction) onto the PC stack—this allows execution to continue, after the
interrupt is serviced, with the next instruction of the main program. The
program sequencer also pushes the current values of the ASTAT, MSTAT,
and IMASK registers onto the status stack. ASTAT, MSTAT and IMASK
are stored in this order, with the MSB of ASTAT first, and so on. When
IMASK is pushed, it is automatically reloaded with a new value that
determines whether or not interrupt nesting is allowed (based on the
value of the interrupt nesting enable bit in ICNTL).
The processor then executes a NOP while simultaneously fetching the
instruction located at the interrupt vector address. Upon return from the
interrupt service routine, the PC and status stacks are popped and
execution resumes with the next instruction of the main program.
3.4.2
The following registers are used to configure interrupts:
• ICNTL—Determines whether interrupts can be nested and configures
the external interrupts IRQ2 , IRQ1 , IRQ0 as edge-sensitive or level-
sensitive
• IMASK—Enables or disables (i.e. masks) each individual interrupt (both
external and internal).
• IFC—Forces an interrupt or clears a pending edge-sensitive interrupt.
The IRQ2 , IRQ1 , IRQ0 interrupts may be either edge-sensitive or level-
sensitive, as selected in the ICNTL register. The ADSP-2181 has three
additional interrupt pins: IRQE , IRQL1 , and IRQL2 . The IRQE input is
edge-sensitive, while the IRQL1 and IRQL2 inputs are level-sensitive.
For edge-sensitive IRQx interrupts, an interrupt request is latched
internally whenever a falling edge (high-to-low transition) occurs at the
input pin. The latch remains set until the interrupt is serviced; it is then
automatically cleared. A pending edge-sensitive interrupt can also be
cleared in software by setting the corresponding clear bit in the IFC
register.
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Interrupt Servicing Sequence

Configuring Interrupts