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Superscalar architectural concept. This is not strictly a superscalar archi-
tecture because the instructions executed in each cycle are specified in the
instruction by the programmer or by the compiler, and not by the chip
hardware. There is also no instruction reordering. Register dependencies
are, however, examined by the hardware and stalls are generated where
appropriate. Code is fully compacted in memory and there are no align-
ment restrictions for instruction lines.
Relative Addresses for Relocation
Most instructions in the TigerSHARC processor support PC relative
branches to allow code to be relocated easily. Also, most data references
are register relative, which means they allow programs to access data blocks
relative to a base register.
Nested Call and Interrupt
Nested call and interrupt return addresses (along with other registers as
needed) are saved by specific instructions onto the on-chip memory stack,
allowing more generality when used with high-level languages. Non-
nested calls and interrupts do not need to save the return address in inter-
nal memory, making these more efficient for short, non-nested routines.
Context Switching
The TigerSHARC processor provides the ability to save and restore up to
eight registers per cycle onto a stack in two internal memory blocks when
using load/store instructions. This fast save/restore capability permits effi-
cient interrupts and fast context switching. It also allows the TigerSHARC
processor to dispense with on-chip PC stack or alternate registers for regis-
ter files or status registers.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Introduction
1-15
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