Interrupts And Sequencing - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Interrupts and Sequencing

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TCOUNT
Also note that
should initialize these registers before enabling the timer.
Interrupts and Sequencing
Another type of nonsequential program flow that the sequencer supports
is interrupt processing. Interrupts may stem from a variety of conditions,
both internal and external to the processor. In response to an interrupt,
the sequencer processes a subroutine call to a predefined address, called
the interrupt vector. The DSP assigns a unique vector to each type of
interrupt and assigns a priority to each interrupt based on the Interrupt
Vector Table (IVT) addressing scheme.
rupt Vector Addresses" in Appendix B, Interrupt Vector Addresses.
The DSP supports three prioritized, individually-maskable external inter-
rupts, each of which can be either level- or edge-sensitive. External
interrupts occur when another device asserts one of the DSP's interrupt
inputs (
IRQ2–0
interrupt can stem from arithmetic exceptions, stack overflows, DMA
completion and/or peripheral data buffer status, or circular data buffer
overflows. Several factors control the DSP's response to an interrupt. The
DSP responds to an interrupt request if:
• the DSP is executing instructions or is in an idle state.
• the interrupt is not masked.
• interrupts are globally enabled.
• a higher priority request is not pending.
When the DSP responds to an interrupt, the sequencer branches program
execution with a call to the corresponding interrupt vector address.
Within the DSP's program memory, the interrupt vectors are grouped in
an area called the Interrupt Vector Table (IVT). The interrupt vectors in
3-48
from and the timer's decrementing of
TPERIOD
and
TCOUNT TPERIOD
). The DSP also supports internal interrupts. An internal
ADSP-2126x SHARC Processor Hardware Reference
are not initialized at reset. Programs
For more information, see "Inter-
.
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