Interrupts; Interrupt I/O Pins; Interrupt Vector Table - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Interrupt I/O Pins

Since it is possible to enter the interrupt service routine (ISR) immediately
after clearing the
This does not affect operation, so it could be used to avoid working the
interrupt.
!
Software interrupts that are caused by a specific instruction must
occur immediately after the instruction that caused them. There-
fore the pipeline is flushed after a software interrupt, and the
instructions that were in the pipeline are not executed.
Interrupt I/O Pins
To issue an interrupt, the Interrupt Request pins,
Each of the
IRQ3-0
level-sensitive. See "Sequencer Control Register – SQCTL" on page 2-16.

Interrupt Vector Table

Each of the interrupts implemented in the TigerSHARC processor has an
interrupt vector register, which is the address of the interrupt routine that
serves the appropriate interrupt. The whole register file (31 entries with
another 32 reserved entries) is referred to as the Interrupt Vector Table
(IVT). The registers are 32 bits each, in order to enable internal and exter-
nal memory interrupt routines.
For boot procedures, some of the interrupt vector registers are initialized
at reset to specific addresses. In boot by EPROM and boot by link opera-
tions, a DMA is initialized to load the boot data into memory address 0x0.
When the boot DMA is executed, it issues a DMA interrupt. The DMA
interrupt vector is also initialized to address 0x0.
4-2
register, the
IMASK
pins may be individually set to either edge triggered or
bit would be 0 while in the ISR.
IMASK
IRQ3-0
ADSP-TS101 TigerSHARC Processor
, are asserted.
Hardware Reference