Table 9.5 Link Service Request Register (Lsrq) - Analog Devices ADSP-2106x SHARC User Manual

This need for masking is due to a delay before LxCLK or LxACK (if
already asserted) signals are pulled (if pulldowns enabled) or driven
externally (if pulldowns disabled) below logic threshold. During this
delay, these signals are sampled asserted and generate an LSRQ.
To avoid the possiblity of spurious interrupts, mask the LSRQ
interrupt or the appropriate request bit in the LSRQ register and allow
an appropriate delay before unmasking. Alternatively, mask the LSRQ
interrupt and poll the appropriate request status bit until it is cleared
and then unmask the interrupt.
Bit Name Description
0-3 reserved
4 L0TM Link Port 0 transmit mask
5 L0RM Link Port 0 receive mask
6 L1TM Link Port 1 transmit mask
7 L1RM Link Port 1 receive mask
8 L2TM Link Port 2 transmit mask
9 L2RM Link Port 2 receive mask
10 L3TM Link Port 3 transmit mask
11 L3RM Link Port 3 receive mask
12 L4TM Link Port 4 transmit mask
13 L4RM Link Port 4 receive mask
14 L5TM Link Port 5 transmit mask
15 L5RM Link Port 5 receive mask
16-19 reserved
20 L0TRQ Link Port 0 transmit request status (read-only)
21 L0RRQ Link Port 0 receive request status (read-only)
22 L1TRQ Link Port 1 transmit request status (read-only)
23 L1RRQ Link Port 1 receive request status (read-only)
24 L2TRQ Link Port 2 transmit request status (read-only)
25 L2RRQ Link Port 2 receive request status (read-only)
26 L3TRQ Link Port 3 transmit request status (read-only)
27 L3RRQ Link Port 3 receive request status (read-only)
28 L4TRQ Link Port 4 transmit request status (read-only)
29 L4RRQ Link Port 4 receive request status (read-only)
30 L5TRQ Link Port 5 transmit request status (read-only)
31 L5RRQ Link Port 5 receive request status (read-only)

Table 9.5 Link Service Request Register (LSRQ)

For transmit request status bits, LxTRQ=1 means LxACK=1, LxTM=1, and LxEN=0.
For receive request status bits, LxRRQ=1 means LxCLK=1, LxRM=1, and LxEN=0.
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