Instruction Completion Latencies - Analog Devices adsp-2100 Manual

latencies exist for all external interrupts. The processor can only service
interrupt or autobuffer requests on instruction cycle boundaries, so there
may be additional latency cycles added due to the completion of an
instruction.

5.13.7 Instruction Completion Latencies

There are several situations which can cause an instruction to take more
than one processor cycle. Any of the following can delay the processor's
ability to service a pending interrupt or autobuffer request:
• External memory wait states
• Bus request when an external access is required (in go-mode)
• Bus request with go-mode disabled
• Multiple external accesses required for a single instruction
Request
CLKOUT
A
EXEC
Figure 5.35 Interrupt Service Example
• A pending higher priority autobuffer or interrupt request
• Interrupt being masked
On instruction cycle boundaries the processor will service multiple pending
interrupt or autobuffer requests in the following priority order:
Request
CLKOUT
A
EXEC
Figure 5.36 Autobuffer Service Example
Serial Ports
B
Sync Delay
NOP Instruction, Fetch Vector
Execute First Instruction Of Interrupt Routine
B
Sync Delay
Do The Autobuffer Transfer
Continue Main Program
FETCH INT INT
AUTOBUFFER C
5
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