Data Cache Access - Analog Devices ADSP-BF53x Blackfin Reference

Figure 6-11 shows an example of how mapping is performed when
.
DCBS = 1
The
DCBS
that no data is lost, first flush and invalidate the entire cache.
Figure 6-11. Data Cache Mapping When DCBS = 1

Data Cache Access

The Cache Controller tests the address from the DAGs against the tag
bits. If the logical address is present in L1 cache, a cache hit occurs, and
the data is accessed in L1. If the logical address is not present, a cache miss
occurs, and the memory transaction is passed to the next level of memory
via the system interface. The line index and replacement policy for the
Cache Controller determines the cache tag and data space that are allo-
cated for the data coming back from external memory.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
selection can be changed dynamically; however, to ensure
8MB
8MB
8MB
8MB
WAY0 WAY1
DATA BANK B
DATA BANK B
WAY0 WAY1
Memory
6-33