Table of Contents
Advertisement
Only one access to each memory block is allowed in each cycle, so DMA
or external port transfers must compete with core accesses on the same
block. Because of the large bandwidth available from each memory block,
not all the memory bandwidth can be used by the core units, which leaves
some memory bandwidth available for use by the processor's DMA pro-
cesses or by the bus interface to serve other DSPs bus master transfers to
the TigerSHARC processor's memory.
Internal Transfer
Most registers of the TigerSHARC processor are classified as universal reg-
isters (Uregs). Instructions are provided for transferring data between any
two Uregs, between a Ureg and memory, or for the immediate load of a
Ureg. This includes control registers and status registers, as well as the
data registers in the register files. These transfers occur with the same tim-
ing as internal memory load/store.
Data Accesses
Each move instruction specifies the number of words accessed from each
memory block. Two memory blocks can be accessed on each cycle because
of the two IALUs.
Quad Data Access
Instructions specify whether one, two, or four words are to be loaded or
stored. Quad-words
2
words
aligned on a long-word boundary. This, however, is not necessary
when loading data to computation units because a data alignment buffer
(DAB) automatically aligns quad-words that are not aligned in memory.
1
A memory quad-word is comprised of four 32-bit words or 128 bits of data.
2
A memory long-word is comprised of two 32-bit words or 64 bits of data.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
1
can be aligned on a quad-word boundary and long-
Introduction
1-17
Advertisement
Table of Contents
