External Memory Access Timing - Analog Devices ADSP-2106x SHARC User Manual

5 Memory
5.5

EXTERNAL MEMORY ACCESS TIMING

Memory access timing for external memory space and multiprocessor
memory space is described below. For exact timing specifications, refer
to the ADSP-2106x Data Sheet.
5.5.1 External Memory
The ADSP-2106x can interface asynchronously, without reference to
CLKIN, to external memories and and memory-mapped peripherals.
In a multiprocessing system, the ADSP-2106x must be the bus master
in order to access external memory.
Figure 5.18 shows representative timing for an asynchronous read or
write of external memory. Note that the clock signal is shown only to
indicate that the access occurs within a single cycle.
5.5.1.1 External Memory Read – Bus Master
External memory reads occur with the following sequence of events
(see Figure 5.18):
1. The ADSP-2106x drives the read address and asserts a memory select
MS
signal (
3-0
not deasserted between successive accesses of the same memory bank.
2. The ADSP-2106x asserts the read strobe (unless the access is aborted
because of a conditional instruction).
3. The ADSP-2106x checks whether wait states are needed. If so, the
memory select and read strobe remain active for additional cycle(s).
Wait states are determined by the state of the external acknowledge
signal (ACK), the internally programmed wait state count, or a
combination of the two.
4. The ADSP-2106x latches in the data.
5. The ADSP-2106x deasserts the read strobe.
6. If initiating another memory access, the ADSP-2106x drives the address
and memory select for the next cycle.
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) to indicate the selected bank. The memory select signal is