Multiplexed Pin Functions; Functional Description; Multiplexed Operation; Address Cycles - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

Pin Descriptions

Multiplexed Pin Functions

The parallel port pins can function as flag pins and the parallel data acqui-
sition port pins can function as address pins. For complete information on
the pin multiplexing scheme used with these processors, see
Pin Multiplexing" on page

Functional Description

This section describes how the parallel port transfers data. The
registers control the parallel port operating mode. The bits in the
PPCTL
register are listed in
SYSCTL
page A-12 lists all the bits in the

Multiplexed Operation

A parallel port multiplexed external transaction consists of a combination
of an address cycle (
section describes the parallel port operation as it relates to processor tim-
ing. Refer to the ADSP-21362/3/4/5/6 SHARC Processor Data Sheet for
detailed timing specifications.

Address Cycles

An cycle is an address latch cycle. It is activated one cycle prior to the
ALE
address. In this cycle the
The upper 16 bits of the address are driven onto the
cycles, and shortly thereafter the
PCLK
remaining valid slightly after deassertion to ensure a sufficient hold time
for the external latch. The
(peripheral clock cycles) irrespective of the data cycle duration values that
are set in the
PPCTL
and so the cycle is 3 x
ALE
upper 16 bits of address differs from a previous access, as well as after the
parallel port is enabled.
4-4
www.BDTIC.com/ADI
14-20.
Table A-1 on page
PPCTL
cycle) and a data cycle (aread or write cycle). This
ALE
and signals are inactive and
RD WR
ALE
pin always remains high for 2 x
ALE
register. The parallel port runs at 1/3 the
. An
PCLK ALE
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
A-4. Table A-3 on
register.
AD15–0
pin is strobed, with
cycle is inserted whenever the
"Parallel Port
and
SYSCTL
is strobed.
ALE
lines for two
AD15–0
,
PCLK
rate,
PCLK