Low-Level Physical Mapping Of Memory Blocks - Analog Devices ADSP-2106x SHARC User Manual

5.3.5.1 Low-Level Physical Mapping Of Memory Blocks

Each block of memory is organized as 16 columns. On the ADSP-21060,
each column contains 8K 16-bit words; on the ADSP-21062, each column
contains 4K 16-bit words. For reads or writes of 48-bit and 32-bit words,
the 13 LSBs of the address select a row from each column. The MSBs of
the address control which columns are selected. For reads or writes of
16-bit short words, the address is right-shifted one place before being
applied to memory (see Figure 5.12). This allows bit 0 of the address to
be used to select between the MSW and LSW of 32-bit data.
When a block is memory is accessed, how many and which columns are
selected depends upon the word width of the access. For 48-bit words,
the 16-bit columns are selected in groups of three and address bits 13-15
determine which group is selected. For 32-bit words, the columns are
selected in groups of two and address bits 13-15 also select the group.
16-bit short word accesses are handled in a slightly different fashion, in
order to provide easy access to the MSW and LSW of 32-bit data. In the
ADSP-2106x's data address generators (DAGs), a single arithmetic right
shift of the short word address gives the physical address of the 32-bit
word being written to. If the bit shifted out is zero, the access is to the
LSW, otherwise it is to the MSW. This is implemented by selecting
columns in groups of two with address bits 13-15 and then selecting
between the two columns in the group with the short word address bit
shifted out.
31 24 17 16 15
1110 0001
Block
Select
Figure 5.12 Preprocessing of 16-Bit Short Word Addresses
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Shift Right
15 13 12
Column
Row Address
Address
Word (16-bit) Select
Memory
0
Short Word Address
0
Physical Address Applied
to Memory Block
High/Low
5
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