Host Address Space - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Memory Access Features
The TigerSHARC processor 32-bit address bus provides an address space
of four gigawords. This address space is common to a cluster of Tiger-
SHARC processors that share the same cluster bus. This chapter defines
the memory map of each TigerSHARC processor in the system and indi-
cates where the memory space defines the location of each element. The
zones in the memory space are made up of the following regions.
• External memory bank space—the region for standard addressing
of off-chip memory (including SDRAM, MB0, MB1, and Host)
• External multiprocessor space—the on-chip memory of all other
TigerSHARC processors connected in a multiprocessor system
• Internal address space—the region for standard internal addressing
The global memory map is shown in Figure 2-1.

Host Address Space

The host address space is the space defined for the host when it is accessed
as a slave. When referring to this space, the pipelined or asynchronous
protocol is used according to the host bits in the
additional information on the
2-2
/ register see Figure 2-9 on
SYSTAT SYSTATCL
ADSP-TS101 TigerSHARC Processor
register—for
SYSTAT
Hardware Reference