Chained Dma - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Chained DMA

Chained DMA allows for the DMA controller to auto-initialize multiple
DMA transfers, thus minimizing loading on the processor core. The chain
pointer field of the DMA control bits points to the address in memory
that contains the address, increment, number of transfers, and control bits
for the next
TCB
DMA transfer completes.
The TigerSHARC DMA controller has a great flexibility of options with
chained DMA sequences.
• Single channel chained DMA
When the chain pointer in the current
to set up another DMA on the same channel.
• Cross channel chained DMA on link ports
When one link port DMA channel sets up a DMA transfer on a
different link port DMA channel.
• Chain insertion
When a high priority DMA operation or another DMA chain may
be inserted into an already active DMA chain.
DMA Architecture
DMA transfers are characterized by the direction of data flow, that is,
from the transmitter (source) to the receiver (destination). If the transmit-
ter or receiver is memory, it is characterized by a
AutoDMA channels have one
one source
TCB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
to be loaded. The new
TCB
register. A receive link or AutoDMA channel has one desti-
Direct Memory Access
is loaded when the current
TCB
points to
TCB
TCB
register each. A transmit channel has
data used
TCB
register. Link and
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