Dma Cycle Stealing, Dma Hold Offs, And Iack - Analog Devices adsp-2100 Manual

11.3.6 DMA Cycle Stealing, DMA Hold Offs, and
IACK
The signal is generated by the ADSP-2181 to signal that it is safe to
read or write through the IDMA port. After reset,
It stays low until an IDMA transfer is initiated. After each IDMA
operation is completed,
IACK
In order for to be asserted (low) during the IDMA operation, the
IDMA port must have completed the internal memory access by either
writing data to memory or reading data from memory. The IDMA port
must "steal" a processor cycle to do this. In order to steal a processor
cycle, the IDMA port must wait for an instruction completion boundary.
IACK
Thus if is not asserted, it is not safe for the host to access the IDMA port.
In most cases, there is an instruction boundary on every clock cycle
(CLKOUT period) and the IDMA port can complete its transfer in a given
period of time. There are, however, some instances where either the
ADSP-2181 does not complete an instruction in one clock cycle or the
IDMA port cannot access memory. These are DMA hold offs:
• Bus Request – If the ADSP-2181 is being held in Bus Request when it
attempts an external access (DM overlay, PM overlay, or I/O memory
space), or if it is not in GO mode, processor execution stops in the
middle of the cycle and no instruction boundary is encountered.
Therefore, the IDMA port cannot complete its internal memory access
IACK
and will be held off.
• External Access with Wait State(s) – If the ADSP-2181 is performing a
wait-stated external access (DM overlay, PM overlay, or I/O memory
space), then the instruction cycle will not complete until the access has
completed; the IDMA port cannot steal a cycle, and
off.
• Multiple External Accesses – If the ADSP-2181 is executing a
multifunction instruction where more than one of the required elements
(PM instruction fetch, PM data access, or DM data access) resides
externally, it will require more than one cycle to complete the
IACK
instruction and
executing an instruction from external PM that initiates an I/O memory
IACK
space access,
• IDLE n (clock-reducing IDLE instruction) – Because this instruction
slows down the effective cycle time of the ADSP-2181,
delayed.
IACK
will again be low.
will be held off. Likewise, if the ADSP-2181 is
will be held off until the cycle completes.
DMA Ports
IACK IACK
IACK IACK IACK
Acknowledge
IACK
is asserted (low).
IACK
will be held
IACK
may be
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