Dma Interrupts - Analog Devices ADSP-2106x SHARC User Manual

6.3.5

DMA Interrupts

When the count register (C) of an active DMA channel decrements to
zero, an interrupt is generated. For the external port DMA channels,
both the C and EC (external count) registers must equal zero before the
interrupt is generated (EC register only in MASTER mode). The count
register(s) must be decremented to zero as a result of actual DMA
transfers in order for a DMA interrupt to be generated—writing zero
to a count register will not generate the interrupt.
Each DMA channel has its own interrupt; the DMA interrupts are
latched in the IRPTL and are enabled in the IMASK register. Table 6.15
shows the IRPTL and IMASK bits of the ten DMA channel interrupts,
in order of priority. (Note: Although the external port channel access
priority can rotate, the interrupt priorities of all DMA channels are
fixed.)
IRPTL/
IMASK Vector Interrupt
1
Bit # Address Name
10 0x28 SPR0I
PRIORITY
11 0x2C SPR1I
12 0x30 SPT0I
13 0x34 SPT1I
14 0x38 LP2I
15 0x3C LP3I
16 0x40 EP0I
17 0x44 EP1I
18 0x48 EP2I
19 0x4C EP3I
PRIORITY
Table 6.15 DMA Interrupt Vectors & Priority
1. Offset from base address: 0x0002 0000 for interrupt vector table in internal
memory, 0x0040 0000 for interrupt vector table in external memory
2. These locations are reserved, not used, on the ADSP-21061.
In addition to IMASK, DMA interrupts for each channel can be
enabled or disabled by the PCI bit of the CP register, when DMA
chaining is enabled. When PCI=1, DMA interrupt requests occur when
the count register reaches zero. When PCI=0, no DMA interrupts are
generated. The PCI bit is valid only when DMA chaining is enabled. If
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DMA Channel Interrupt
DMA Channel 0 – SPORT0 Receive
DMA Channel 1 – SPORT1 Receive (or Link Buffer 0)
DMA Channel 2 – SPORT0 Transmit
DMA Channel 3 – SPORT1 Transmit (or Link Buffer 1)
DMA Channel 4 – Link Buffer 2
DMA Channel 5 – Link Buffer 3
DMA Channel 6 – Ext. Port Buffer 0 (or Link Buffer 4)
DMA Channel 7 – Ext. Port Buffer 1 (or Link Buffer 5)
DMA Channel 8 – Ext. Port Buffer 2
DMA Channel 9 – Ext. Port Buffer 3
DMA 6
HIGHEST
2
2
2
2
LOWEST
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