External Port Dma Control Registers - Analog Devices ADSP-2106x SHARC User Manual

31 30 29 28 27
0
15 14 13 12
0
FS
Ext. Port FIFO Buffer Status
00=empty, 10=partially full, 11=full
FLSH
Flush Ext. Port FIFO Buffer
1=flush
EXTERN
Ext. Devices to Ext. Memory DMA
1=extern mode
INTIO
Single-Word Interrupts for
Ext. Port FIFO Buffers
1=enable, 0=disable
HSHAKE
DMA Handshake
1=enable, 0=disable
MASTER
DMA Master Mode
1=enable, 0=disable
MSWF
Most Significant Word First
for Packing
1=enable, 0=disable
Figure 6.3 DMACx Registers
6.2.1

External Port DMA Control Registers

Each external port DMA channel has its own control register. The registers
are named DMAC6, DMAC7, DMAC8, and DMAC9, corresponding to
channels 6-9. Note that for the ADSP-21061 only DMA channels 6 and 7 of
the external port are applicable. Table 6.3 shows the contents of the
DMACx registers. All bits are active high unless stated otherwise.
The control bits in the DMACx registers take effect during the second
cycle after the write to the register is completed. The exception to this rule
is the FLSH bit, which takes effect in the third cycle after the write.
To start a new DMA sequence after the current one is finished, your
program must first clear the DEN enable bit, write new parameters to the
II, IM, and C registers, and then set the DEN bit to re-enable DMA. (For
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26 25 24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0 0
11 10 9 8 7 6
0 0 0 0 0 0 0 0 0
DMA
16
0 0 0 0 0 0
5 4 3 2 1 0
0 0 0 0 0 0
DEN
DMA Enable for Ext. Port
1=enable, 0=disable
CHEN
DMA Chaining Enable for Ext. Port
1=enable, 0=disable
TRAN
DMA Channel Direction
0=read from ext. memory
1=write to ext. memory
PS
Packing Status (read-only)
00=packing complete
01=1st stage of all pack & unpack modes
10=2nd stage of 16-to-48 bit pack/unpack,
or 2nd stage of 32-to-48 pack/unpack
DTYPE
Data Type
0=data, 1=instructions
PMODE
Packing Mode
00=no packing
01=16/32
10=16/48
11=32/48
6
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