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SERIAL PORT TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 5.
Parameter
WRITE OPERATION (See Figure 46)
SCLK Clock Rate (f
)
SCLK
SCLK Clock High (t
)
HI
SCLK Clock Low (t
)
LOW
SDIO to SCLK Setup Time (t
SCLK to SDIO Hold Time (t
DH
SEN to SCLK Setup Time (t
S
SCLK to SEN Hold Time (t
)
H
READ OPERATION (See Figure 47 and Figure 48)
SCLK Clock Rate (f
)
SCLK
SCLK Clock High (t
)
HI
SCLK Clock Low (t
)
LOW
SDIO to SCLK Setup Time (t
SCLK to SDIO Hold Time (t
DH
SCLK to SDIO (or SDO) Data Valid Time (t
SEN to SDIO Output Valid to Hi-Z (t
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 6.
Parameter
1
READ OPERATION
(See Figure 50)
Output Data Rate
Three-State Output Enable Time (t
Three-State Output Disable Time (t
Rx Data Valid Time (t
)
VT
Rx Data Output Delay (t
)
OD
WRITE OPERATION (See Figure 49)
Input Data Rate (1× Interpolation)
Input Data Rate (2× Interpolation)
Input Data Rate (4× Interpolation)
Tx Data Setup Time (t
)
DS
Tx Data Hold Time (t
)
DH
Latch Enable Time (t
)
EN
Latch Disable Time (t
)
DIS
1
C
= 5 pF for digital data outputs.
LOAD
)
DS
)
)
)
DS
)
)
DV
)
EZ
)
PZL
)
PLZ
Temp
Test Level
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Temp
Test Level
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Rev. A | Page 7 of 48
Min
Typ
Max
32
14
14
14
0
14
0
32
14
14
14
0
14
2
Min
Typ
Max
5
80
3
3
1.5
4
20
80
10
80
5
50
1
2.5
3
3
AD9866
Unit
MHz
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
Unit
MSPS
ns
ns
ns
ns
MSPS
MSPS
MSPS
ns
ns
ns
ns
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