Bus Timeout Protection; Similarity Between Pmbus, Smbus And I 2 C 2-Wire Interface; Pmbus Serial Digital Interface - Analog Devices LTM4683 Manual

LTM4683
OPERATION

BUS TIMEOUT PROTECTION

The LTM4683 implements a timeout feature to avoid
persistent faults on the serial interface. The data packet
timer begins at the first START event before the device
address byte write. Data packet information must be
completed within 30ms, or the LTM4683 will three-state
the bus and ignore the given data packet. If more time
is required, assert bit 3 of MFR_CONFIG_ALL to allow
typical bus timeouts of 255ms. Data packet information
includes the device address byte write, command byte,
repeat start event (if a read operation), device address
byte read (if a read operation), all data bytes and the PEC
byte if applicable.
The LTM4683 allows longer PMBus timeouts for block-
read data packets. This timeout is proportional to the
length of the block read. The additional block read timeout
applies primarily to the MFR_FAULT_LOG command. The
timeout period defaults to 32ms.
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTM4683
supports the full PMBus frequency range from 10kHz
to 400kHz.
SIMILARITY BETWEEN PMBus, SMBus AND I
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple I
byte commands because PMBus/SMBus provide time-
outs to prevent persistent bus errors and optional packet
error checking (PEC) to ensure data integrity. In general,
a main device that can be configured for I
tion can be used for PMBus communication with little or
no change to hardware or firmware. Repeat start (restart)
2
is not supported by all I
SMBus/PMBus reads. If a general-purpose I
is used, check that repeat start is supported.
The LTM4683 supports the maximum SMBus clock
speed of 100kHz and is compatible with the higher speed
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C with some minor
2
C communica-
C controllers but is required for
2
C controller
For more information
PMBus specification (between 100kHz and 400kHz) if
MFR_COMMON polling or clock stretching is enabled.
For robust communication and operation, see the Note
section in the PMBus command summary table (See
Table 7). Clock stretching is enabled by asserting bit 1 of
MFR_CONFIG_ALL.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, Refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
To describe the differences between SMBus and I
refer to System Management Bus (SMBus) Specification
Version 2.0: Appendix B—Differences Between SMBus
2
and I C.

PMBus SERIAL DIGITAL INTERFACE

The LTM4683 communicates with a host (main) device
using the standard PMBus serial bus interface. The tim-
ing diagram, Figure 6, shows the timing relationship of
the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-
up resistors or current sources are required on these
lines. The LTM4683 is a subordinate device. The main
device can communicate with the LTM4683 using the
following formats:
The Main Transmitter, Subordinate Receiver
n
The Main Receiver, Subordinate Transmitter
n
The following PMBus protocols are supported:
Write Byte, Write Word, Send Byte
n
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Read Byte, Read Word, Block Read, Block Write
n
Alert Response Address
n
Figure 7—Figure 24 illustrate the aforementioned PMBus
protocols. All transactions support PEC and GCP (group
command protocol). The Block Read supports 255 bytes
of returned data. For this reason, the PMBus timeout may
be extended when reading the fault log.
Figure 7 is the key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in Figure 7—Figure 24 is a
mandatory value for that field.
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