On-Chip Registers - Analog Devices AD7194 Manual

AD7194

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set,
implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.
Table 15. Register Summary
Register Addr.
Communications 00
Status 00
Mode 01
Configuration 02
Data 03
ID 04
GPOCON 05
Offset 06
Full Scale 07
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Dir. Default Bit 7
W 00 0
R 80 RDY
R/W 080060 Mode select
SINC3
FS7
R/W 000117 Chop (MSB)
CH7(
Burn
R 000000 D23 (MSB)
D15
D7
R X3 X
R/W 00 0
R/W 800000 OF23 (MSB)
OF15
OF7
R/W 5XXXX0 FS23 (MSB)
FS15
FS7
Bit 6 Bit 5 Bit 4
R/W Register address
ERR NOREF Parity
DAT_STA
0 ENPAR CLK_DIV
FS6 FS5 FS4
0 0 REFSEL
CH6 CH5 CH4
REFDET 0 BUF
D22 D21 D20
D14 D13 D12
D6 D5 D4
X X X
0 GP32EN GP10EN
OF22 OF21 OF20
OF14 OF13 OF12
OF6 OF5 OF4
FS22 FS21 FS20
FS14 FS13 FS12
FS6 FS5 FS4
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Bit 3 Bit 2 Bit 1 Bit 0
CREAD 0 0
CHD3 CHD2 CHD1 CHD0
CLK1 CLK0 AVG1 AVG0
Single REJ60 FS9 FS8
FS3 FS2 FS1 FS0 (LSB)
0 Pseudo 0 TEMP
CH3 CH2 CH1 CH0
U/B G2 G1 G0 (LSB)
D19 D18 D17 D16
D11 D10 D9 D8
D3 D2 D1 D0 (LSB)
0 0 1 1
P3DAT P2DAT P1DAT P0DAT
OF19 OF18 OF17 OF16
OF11 OF10 OF9 OF8
OF3 OF2 OF1 OF0 (LSB)
FS19 FS18 FS17 FS16
FS11 FS10 FS9 FS8
FS3 FS2 FS1 FS0 (LSB)