Spi Registers - Analog Devices AD9739 Manual

AD9739
Name Address Bit 7
LVDS_ 0x1F SYNCSH_
DEL[0]
REC_STAT7
LVDS_ 0x20 SYNCSH_
DEL[8]
REC_STAT8
LVDS_ 0x21 SYNC_TRK
_ON
REC_STAT9
CROSS_ 0x22 N/A
CNT1
CROSS_ 0x23 N/A
CNT2
PHS_DET 0x24 N/A
MU_DUTY 0x25 MU_DUTY
AUTO_EN
MU_CNT1 0x26 N/A
MU_CNT2 0x27 MUDEL[0]
MU_CNT3 0x28 MUDEL[8]
MU_CNT4 0x29 Search_Tol
MU_STAT1 0x2A N/A
RSVD 0x2B N/A
RSVD 0x2C N/A
ANA_CNT1 0x32 HDRM[7]
ANA_CNT2 0x33 N/A
RSVD 0x34 N/A
PART ID 0x35 ID[7]

SPI REGISTERS

Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 8. Mode Register (Register 0x00)
Register
1
Name Address
Mode 0x00
1
The two-digit number is the decimal representation of the address.
Table 9. Mode Register Bit Descriptions
Bit
Name Read/Write Description
SDIO_DIR Read/write 0: input only, per SPI standard.
1: bidirectional, per SPI standard.
LSB/MSB Read/write 0: MSB first, per SPI standard.
1: LSB first, per SPI standard.
Change the LSB/MSB order in single-byte instructions only to avoid erratic behavior due to
bit order errors.
Reset Read/write 0: default. Bit is in the inactive state.
1: all programmable bits return to their default state except Register 0x00, which is
unaffected by the software reset. The software reset remains in effect until this bit is set to 0
(inactive state).
Table 10. Power-Down Register (Register 0x01)
Register
1
Name Address
Power-Down 0x01 01
1 The two-digit number is the decimal representation of the address.
Bit 6 Bit 5
N/A N/A
SYNCSH_ SYNCSH_
DEL[7] DEL[6]
SYNC_INIT SYNC_LST
_ON _LCK
N/A N/A
N/A N/A
N/A PHS_DET
AUTO_EN
POS/NEG ADJ[5]
Slope Mode[1]
SrchMode SrchMode
[1] [0]
MUDEL[7] MUDEL[6]
Retry ContRst
N/A N/A
N/A N/A
N/A N/A
HDRM[6] HDRM[5]
N/A N/A
N/A N/A
ID[6] ID[5]
Bit 7 Bit 6
00 SDIO_DIR LSB/MSB
Bit 7 Bit 6 Bit 5
N/A N/A LVDS_DCO_PD
Bit 4 Bit 3
N/A N/A
SYNCSH_ SYNCSH_
DEL[5] DEL[4]
SYNC_LCK RCVR_TRK
_ON
DIR_P CLKP_
OFFSET[3]
DIR_N CLKN_
OFFSET[3]
CMP_BST Bias[3]
ADJ[4] ADJ[3]
Mode[0] Read
SetPhs[4] SetPhs[3]
MUDEL[5] MUDEL[4]
Guard[4] Guard[3]
N/A N/A
N/A N/A
N/A N/A
HDRM[4] HDRM[3]
N/A N/A
N/A N/A
ID[4] ID[3]
Bit 5 Bit 4
Reset N/A
Bit 4 Bit 3
LVDS_RCVR_PD N/A
Rev. A | Page 28 of 56
Bit 2 Bit 1 Bit 0
N/A N/A N/A
SYNCSH_ SYNCSH_ SYNCSH_
DEL[3] DEL[2] DEL[1]
RCVR_FE_ RCVR_LST_ RCVR_LCK
ON LCK
CLKP_ CLKP_ CLKP_
OFFSET[2] OFFSET[1] OFFSET[0]
CLKN_ CLKN_ CLKN_
OFFSET[2] OFFSET[1] OFFSET[0]
Bias[2] Bias[1] Bias[0]
ADJ[2] ADJ[1] ADJ[0]
Gain[1] Gain[0] Enable
SetPhs[2] SetPhs[1] SetPhs[0]
MUDEL[3] MUDEL[2] MUDEL[1]
Guard[2] Guard[1] Guard[0]
N/A MU_LOST MU_LKD
N/A N/A N/A
N/A N/A N/A
HDRM[2] HDRM[1] HDRM[0]
N/A MSEL[1] MSEL[0]
N/A N/A N/A
ID[2] ID[1] ID[0]
Bit 3 Bit 2
N/A N/A
Bit 2 Bit 1
N/A CLK_REC_PD
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x42
0x40
0x00
0x0B
0x00
N/A
N/A
0xCA
0x03
N/A
0x40
Bit 1 Bit 0
N/A N/A
Reset Value for
Write Register
0
0
0
Bit 0
DAC_BIAS_PD