Dma Control Registers - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Control and Status Registers

DMA Control Registers

There are three DMA control registers—
DCNT Register
This 32-bit control register controls the DMA flow. Setting
DMA flow at the end of the current transaction; clearing
resumes a suspended transaction. Initial value of the
0x0.
Figure 7-14. DCNT (Upper) Register
7-26
DCNT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
PA13
PA12
ADSP-TS101 TigerSHARC Processor
, and
DCNTST, DCNTCL
DCNT
bits
DCNT
after reset is
DCNT
Hardware Reference
.
bits stop