Standard Dma Parameter Registers - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

IOP Registers

Standard DMA Parameter Registers

The parameter registers described below control the source and destina-
tion of the data, the size of the data buffer, and the step size used.
Index registers. Shown in
acting as a pointer to the next internal memory DMA read or write loca-
tion. All internal index addresses are based on an internal memory offset
of 0x80000.
Table 2-2. Index Registers
Register Name
IISP0–5A
IISP0–5B
IISPI
IISPIB
IDP_DMA_I0–7
IDP_DMA_I0–7A
IDP_DMA_I0–7B
IIMTMW
IIMTMR
IIPP
EIPP
Modify registers. Shown in
which the DMA controller post-modifies the corresponding memory
index register after the DMA read or write.
2-6
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Table 2-2, provide an internal memory address,
Width (Bits) Description
19 SPORTA
19 SPORTB
19 SPI
19 SPIB
19 IDP
19 IDP index A (ping pong)
19 IDP index B (ping pong)
19 MTM Write
19 MTM Read
19 Parallel Port
24 Parallel Port (external address)
Table 2-3, provide the signed increment by
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors