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Interrupt Controller
Just as the core has its own interrupt latch registers (
the DAI has its own latch registers (
a DAI interrupt is configured to be high priority, it is latched in the
register. When any bit in the
DAI_IRPTL_H
(= 1), bit 11 in the
interrupt with high priority. When a DAI interrupt is configured to be
low priority, it is latched in the
bit in the
DAI_IRPTL_L
also set and the core services that interrupt with low priority.
By default, interrupts are mapped onto a low priority interrupt.
Miscellaneous Interrupts
As described above, the DAI interrupt controller registers provide 10 inde-
pendently-configurable interrupts labeled as
on the DAI inputs
SRU_MISCx_INT
Signals from the SRU can also be used to generate interrupts. For exam-
ple, when
SRU_EXTMISCA2_INT
signals from the external miscellaneous channel 2 generate an interrupt,
the DAI interrupts trigger an interrupt in the core and the interrupt latch
is set. A read of this bit does not reset it to zero. The bit is only set to zero
when the cause of the interrupt is cleared. A DAI interrupt indicates the
source (in this case, external miscellaneous A, channel 2), and checks the
IVT for an instruction (next operation) to perform.
Core versus DAI Interrupts
In the ADSP-2136x processor, a pair of registers (
) replace functions normally performed by the
DAI_IRPTL_L
A single register (
are mapped.
5-26
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register is also set and the core services that
IRPTL
DAI_IRPTL_L
register is set (= 1), bit 6 in the
can cause an interrupt latch event in
DAI_INTx_I
if enabled.
(bit 30) of
) specifies to which latch these interrupts
DAI_IRPTL_PRI
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
IRPTL
and
DAI_IRPTL_L
DAI_IRPTL_H
DAI_IRPTL_H
register. Similarly, when any
SRU_MISCx_INT
DAI_IRPTL_H
DAI_IRPTL_H
and
),
LIRPTL
). When
register is set
register is
LIRPTL
. Any trigger
is set (= 1), any
and
register.
IRPTL
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