Dai Interrupts - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

DAI Interrupt Controller

DAI Interrupts

There are several registers in the DAI Interrupt Controller that can be
configured to control how the DAI interrupts are reported to and serviced
by the core's Interrupt Controller. Among other options, each DAI inter-
rupt can be mapped either as a high or low priority interrupt in the
primary interrupt controller, certain DAI interrupts can be triggered on
either the rising or falling edge of signals, and each DAI interrupt can also
be independently masked.
Just as the core has its own interrupt latch registers (
the DAI has its own latch registers (
a DAI interrupt is configured to be high priority, it is latched in the
register. When any bit in the
DAI_IRPTL_H
(= 1), bit 11 in the
interrupt with high priority. When a DAI interrupt is configured to be
low priority, it is latched in the
bit in the
DAI_IRPTL_L
also set and the core services that interrupt with low priority. Regardless of
the priority, when a DAI interrupt is latched and promoted to the core
interrupt latch, the ISR must query the DAI's Interrupt Controller to
determine the source(s). Sources can be any one or more of the Interrupt
Controller's 32-configurable channels (
mation, see "DAI Interrupt Controller Registers" on page A-167.

Reading the DAI's interrupt latches clears them. Therefore, the
ISR must service all the interrupt sources it discovers. That is, if
multiple interrupts are latched in one of the
all of them must be serviced before executing an

The
IDP_FIFO_GTN_INT
DAI_IRPTL_H/L
ically when the situation that caused of the interrupt goes away.
12-28
DAI_IRPTL_L
register is also set and the core services that
IRPTL
DAI_IRPTL_L
register is set (= 1), bit 6 in the
interrupt is not cleared when the
registers are read. This interrupt is cleared automat-
ADSP-2126x SHARC Processor Hardware Reference
IRPTL
and
DAI_IRPTL_H
register is set
DAI_IRPTL_H
register. Similarly, when any
LIRPTL
). For more infor-
DAI_INT[31:0]
DAI_IRPTL_x
RTI
and ),
LIRPTL
). When
register is
registers,
instruction.