Timing Specifications - Analog Devices AD5100 Manual

TIMING SPECIFICATIONS

Table 3.
Parameter
2
I C INTERFACE TIMING CHARACTERISTICS
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1 Guaranteed by design and not subject to production test.
2
See Figure 2.
SCL
SDA
t
1
P S
Description
1, 2
SCL clock frequency
t , bus free time between start and stop
BUF
t , hold time after (repeated) start condition; after this
HD;STA
period, the first clock is generated
t , low period of SCL clock
LOW
t , high period of SCL clock
HIGH
t , setup time for start condition
SU;STA
t , data hold time
HD;DAT
t , data setup time
SU;DAT
t , fall time of both SDA and SCL signals
F
t , rise time of both SDA and SCL signals
R
t , setup time for stop condition
SU;STO
t t
8 6
t t
2 3
t
9
t
8
Figure 2. Digital Interface Timing Diagram
t
9
t t
4 7
S
Rev. A | Page 7 of 36
Min
1.3
0.6
1.3
0.6
0.6
0.1
0.6
t
2
t
5
AD5100
Typ Max Unit
400 kHz
μs
μs
μs
50 μs
μs
0.9 μs
μs
0.3 μs
0.3 μs
μs
t
10
P