General Specifications; Timing Characteristics - Analog Devices ADF7021-V Manual

ADF7021-V

GENERAL SPECIFICATIONS

Table 5.
Parameter
TEMPERATURE RANGE (T )
A
POWER SUPPLIES
Voltage Supply, V
DD
TRANSMIT CURRENT CONSUMPTION
868 MHz
0 dBm
5 dBm
10 dBm
460 MHz
0 dBm
5 dBm
10 dBm
RECEIVE CURRENT CONSUMPTION
868 MHz
Low Current Mode
High Sensitivity Mode
460 MHz
Low Current Mode
High Sensitivity Mode
POWER-DOWN CURRENT CONSUMPTION
Low Power Sleep Mode
1
The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards.
Improved PA efficiency is achieved by using a separate PA matching network.
2 Device current only. VCO and TCXO currents are excluded.

TIMING CHARACTERISTICS

V = 3 V ± 10%, GND = 0 V, T
DD
Table 6.
Parameter Limit at T
t >10
1
t >10
2
t >25
3
t >25
4
t >10
5
t >20
6
t <25
8
t <25
9
t >10
10
t 5 < t < (¼ × t
11 11
t >5
12
t >5
13
t 5 < t < (¼ × t
14 14
t >¼ × t
15 BIT
Min
−40
2.3
1, 2
2
2
= 25°C, unless otherwise noted. Guaranteed by design but not production tested.
A
to T Unit
MIN MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
) ns
BIT
ns
ns
) μs
BIT
μs
Typ Max Unit
+85 °C
3.6 V
17.6 mA
20.8 mA
27.1 mA
13.8 mA
17 mA
23 mA
19.3 mA
21.7 mA
16.3 mA
18.3 mA
0.1 1 μA
Description
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
SLE pulse width
SCLK to SREAD data valid, readback
SREAD hold time after SCLK, readback
SCLK to SLE disable time, readback
TxRxCLK negative edge to SLE
TxRxDATA to TxRxCLK setup time (Tx mode)
TxRxCLK to TxRxDATA hold time (Tx mode)
TxRxCLK negative edge to SLE
SLE positive edge to positive edge of TxRxCLK (Rx mode)
Rev. 0 | Page 10 of 60
Test Conditions/Comments
All VDDx pins must be tied together
V = 3.0 V, PA is matched into 50 Ω
DD
V = 3.0 V
DD
CE low