Timing Characteristics - Analog Devices AD9830 Instruction Manual

TIMING CHARACTERISTICS

Limit at
T to T
MIN
Parameter (A Version)
t 20
1
t 8
2
t 8
3
1
t 8
4
1
t 8
4A
t 8
5
t t
6 1
t 5
7
t 3
8
1
t 8
9
1
t 8
9A
t t
10 1
NOTES
1
See Pin Description section.
Guaranteed by design, but not production tested.
MCLK
WR
WR
A0, A1, A2
DATA
MCLK
FSELECT
PSEL0, PSEL1
RESET
REV. B
(V = +5 V 5%; AGND = DGND = 0 V, unless otherwise noted)
DD
MAX
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
1
t t
2 3
t
4A
Figure 2. WR –MCLK Relationship
t
5
Figure 3. Writing to a Phase/Frequency Register
VALID DATA
Figure 4. Control Timing
Test Conditions/Comments
MCLK Period
MCLK High Duration
MCLK Low Duration
WR Rising Edge Before MCLK Rising Edge
WR Rising Edge After MCLK Rising Edge
WR Pulse Width
Duration Between Consecutive WR Pulses
Data/Address Setup Time
Data/Address Hold Time
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
RESET Pulse Duration
t
6
t
6
t
8
t
7
VALID DATA
t
9
VALID DATA
t
10
–3–
AD9830
t
4
t
5
VALID DATA
t
9A
VALID DATA