Digital Timing Specifications - Analog Devices ADAU1961 Manual

DIGITAL TIMING SPECIFICATIONS

−40°C < T < +105°C, IOVDD = 3.3 V ± 10%.
A
Table 6. Digital Timing
Parameter
MASTER CLOCK
t
MP
t
MP
t
MP
t
MP
SERIAL PORT
t
BIL
t
BIH
t
LIS
t
LIH
t
SIS
t
SIH
t
SODM
SPI PORT
f
CCLK
t
CCPL
t
CCPH
t
CLS
t
CLH
t
CLPH
t
CDS
t
CDH
t
COD
2
I C PORT
f
SCL
t
SCLH
t
SCLL
t
SCS
t
SCH
t
DS
t
SCR
t
SCF
t
SDR
t
SDF
t
BFT
DIGITAL MICROPHONE
t
DCF
t
DCR
t
DDV
t
DDH
Downloaded from Elcodis.com electronic components distributor
Limit
t t Unit
MIN MAX
74 488 ns
37 244 ns
24.7 162.7 ns
18.5 122 ns
5 ns
5 ns
5 ns
5 ns
5 ns
5 ns
50 ns
10 MHz
10 ns
10 ns
5 ns
10 ns
10 ns
5 ns
5 ns
50 ns
400 kHz
0.6 μs
1.3 μs
0.6 μs
0.6 μs
100 ns
300 ns
300 ns
300 ns
300 ns
0.6 μs
10 ns
10 ns
22 30 ns
0 12 ns
Rev. 0 | Page 9 of 76
Description
MCLK period, 256 × f mode.
S
MCLK period, 512 × f mode.
S
MCLK period, 768 × f mode.
S
MCLK period, 1024 × f mode.
S
BCLK pulse width low.
BCLK pulse width high.
LRCLK setup. Time to BCLK rising.
LRCLK hold. Time from BCLK rising.
DAC_SDATA setup. Time to BCLK rising.
DAC_SDATA hold. Time from BCLK rising.
ADC_SDATA delay. Time from BCLK falling in master mode.
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT three-stated. Time from CLATCH rising.
SCL frequency.
SCL high.
SCL low.
Setup time; relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time. Time between stop and start.
R = 1 MΩ, C = 14 pF.
LOAD LOAD
Digital microphone clock fall time.
Digital microphone clock rise time.
Digital microphone delay time for valid data.
Digital microphone delay time for data three-stated.
ADAU1961