Timing Specifications; Serial Ports - Analog Devices ADAV4622 Manual

TIMING SPECIFICATIONS

Table 2.
Parameter
MASTER CLOCK AND RESET
f
MCLKI
t
MCH
t
MCL
t
RESET
MASTER CLOCK OUTPUT
t
JIT
t
CH
t
CL
2
I C PORT
f
SCL
t
SCLH
t
SCLL
Start Condition
t
SCS
t
SCH
t
DS
t
SCR
t
SCF
t
SDR
t
SDF
Stop Condition
t
SCS

SERIAL PORTS

Slave Mode
t
SBH
t
SBL
f
SBF
t
SLS
t
SLH
t
SDS
t
SDH
t
SDD
Master Mode
t
MLD
t
MDD
t
MDS
t
MDH
Description Min
MCLKI frequency 3.072
MCLKI high 10
MCLKI low 10
RESET low 200
Period jitter
MCLK_OUT high 45
MCLK_OUT low 45
SCL clock frequency
SCL high 600
SCL low 1.3
Setup time 600
Hold time 600
Data setup time 100
SCL rise time
SCL fall time
SDA rise time
SDA fall time
Setup time 0
BCLK high 40
BCLK low 40
BCLK frequency 64 × f
LRCLK setup 10
LRCLK hold 10
SDIN setup 10
SDIN hold 10
SDO delay
LRCLK delay
SDO delay
SDIN setup 10
SDIN hold 10
Max Unit
24.576 MHz
ns
ns
ns
800 ps
55 %
55 %
400 kHz
ns
μs
ns
ns
ns
300 ns
300 ns
300 ns
300 ns
ns
ns
ns
S
ns
ns
ns
ns
50 ns
25 ns
15 ns
ns
ns
Rev. B | Page 9 of 28
ADAV4622
Comments
Relevant for repeated start condition
After this period, the first clock is generated
To BCLK rising edge
From BCLK rising edge
To BCLK rising edge
From BCLK rising edge
From BCLK falling edge
From BCLK falling edge
From BCLK falling edge
From BCLK rising edge
From BCLK rising edge