Timing Parameters - Analog Devices ADSP-21020 Specification Sheet

TIMING PARAMETERS

General Notes
See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters
from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the
values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to
derive other specifications.
Clock Signal
Parameter
Timing Requirement:
t CLKIN Period
CK
t CLKIN Width High
CKH
t CLKIN Width Low
CKL
Reset
Parameter
Timing Requirement:
1
t RESET Width Low
WRST
2
t RESET Setup before CLKIN High 29
SRST
NOTES
DT = t –50 ns
CK
1
Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles while RESET is low,
assuming stable V and CLKIN (not including clock oscillator start-up time).
DD
2
Specification only applies in cases where multiple ADSP-21020 processors are required to execute in program counter lock-step (all processors start execution at
location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User's Manual for reset sequence information.
CLKIN
RESET
REV. C
K/B/T Grade K/B/T Grade
20 MHz 25 MHz
Min Max Min
50 150 40
10 10
10 10
t
CLKIN
t
CKH
Figure 3. Clock
K/B/T Grade K/B/T Grade B/T Grade
20 MHz 25 MHz
Min Max Min Max
200 160
50 24 40
t
WRST
Figure 4. Reset
–13–
B/T Grade
30 MHz
Max Min Max
150 33 150
10
10
CK
t
CKL
K Grade
30 MHz 33.3 MHz
Min Max Min Max
132 120
21 33 19 30
t
SRST
ADSP-21020
K Grade
33.3 MHz
Min Max Unit
30 150 ns
10 ns
10 ns
Frequency Dependency*
Min Max Unit
4t ns
CK
29 + DT/2 30 ns