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Operating Modes
Note that the SPORT DMA controller typically keeps the transmit buffer
full. The application is responsible for filling the transmit buffers with
data.
Operating Modes
The following sections provide detailed information on each operating
mode available using the serial ports. It should be noted that many bits in
the SPORT registers that control the function of the mode are the same
bit but have a different name depending on the operating mode. Further,
some bits are used in some modes but not others. For reference, see
Table 6-4 on page
Control Registers (SPCTLx)" on page
Standard Serial Mode
The standard serial mode lets programs configure serial ports for use by a
variety of serial devices such as serial data converters and audio codecs.
more information, see Appendix C, Audio Frame Formats.
Timing Control Bits
Several bits in the
serial mode operation:
• Operation mode
• Frame Sync Channel First (
• Frame Sync Required (
• Internal Frame Sync (
• Sampling Edges Frame Sync/data (
• Logic Level Frame Sync (
6-34
www.BDTIC.com/ADI
6-11,
Table 6-5 on page
control register enable and configure standard
SPCTLx
= 0 (standard serial mode)
OPMODE
LFS
)
FSR
)
IFS
)
LFS
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
6-19, and
"SPORT Serial
A-30.
)
)
CKRE
For
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