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Signal Name
FPGA Pin No.
PS2_CLK
PIN_G6
PS2_DAT
PIN_H5
PS2_CLK2
PIN_G5
PS2_DAT2
PIN_F5
4
.
1
4
G
i
g
a
b
i
t
4
.
1
4
G
i
g
a
b
i
t
The DE2-115 board provides Ethernet support via two Marvell 88E1111 Ethernet PHY chips. The
88E1111 chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver support
GMII/MII/RGMII/TBI MAC interfaces.
Figure 4-27
shows the connection setup between the Gigabit Ethernet PHY (ENET0) and FPGA.
Configuration
Description
PHYADDR[4:0]
PHY Address in MDIO/MDC Mode 10000 for Enet0;10001 for Enet1
ENA_PAUSE
Enable Pause
Auto negotiation configuration
ANEG[3:0]
for copper modes
ENA_XC
Enable Crossover
DIS_125
Disable 125MHz clock
HWCFG[3:0]
Hardware Configuration Mode
DIS_FC
Disable fiber/copper interface
DIS_SLEEP
Energy detect
SEL_TWSI
Interface select
INT_POL
Interrupt polarity
75/50OHM
Termination resistance
Here only RGMII and MII modes are supported on the board (The factory default mode is RGMII).
There is one jumper for each chip for switching work modes from RGMII to MII (See
Figure 4-26 Y-Cable use for both Keyboard and Mouse
Table 4-19 PS/2 Pin Assignments
Description
PS/2 Clock
PS/2 Data
PS/2 Clock (reserved for second PS/2 device)
PS/2 Data (reserved for second PS/2 device)
E
t
h
e
r
n
e
t
T
E
t
h
e
r
n
e
t
T
Table 4-20 Default Configuration for Gigabit Ethernet
r
a
n
s
c
e
i
v
e
r
r
a
n
s
c
e
i
v
e
r
Table 4-20
describes the default settings for both chips.
Default Value
1-Default Register 4.11:10 to 11
1110-Auto-neg, advertise all capabilities, prefer
master
0-Disable
1-Disable 125CLK
1011/1111 RGMII to copper/GMII to copper
1-Disable
1-Disable energy detect
0-Select MDC/MDIO interface
1-INTn signal is active LOW
0-50 ohm termination for fiber
56
I/O Standard
3.3V
3.3V
3.3V
3.3V
Figure
4-28).
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