Ethernet Mac/Phy (U16) - Altera Stratix II Reference Manual

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Board Components & Interfaces
Altera Corporation
August 2006
Table 22. SDRAM Device (U40) Pin-Outs (Part 3 of 3)
Pin Name
Pin Number
DQM3
RAS_N
CAS_N
CKE
CS_N
Table 23
lists the reference information for the SDRAM memory.
Table 23. SDRAM Memory Reference
Item
Board reference
Device description

Ethernet MAC/PHY (U16)

The LAN91C111 (U16) is a mixed signal analog/digital device that
implements protocols at 10 Mbps and 100 Mbps. The control pins of U16
are connected to the Stratix II device so that user logic (e.g., the Nios II
processor) can access Ethernet via the RJ-45 connector (RJ1). Refer to
Table 24
for Stratix II pin-outs for Ethernet MAC/PHY device U16.t
Table 24. Ethernet MAC/PHY (U16) (Part 1 of 3)
Pin Name
ENET_ADS_N
ENET_AEN
ENET_BE_N0
ENET_BE_N1
ENET_BE_N2
ENET_BE_N3
ENET_DATACS_N
ENET_INTRQ0
ENET_IOCHRDY
ENET_IOR_N
ENET_IOW_N
Reference Manual
Connects to Stratix II Pin
59
AC12
19
AK4
18
AL8
67
AL7
20
AL6
Description
U39, U40
SDRAM Memory
Pin Number
AA25
AC25
AE26
AE25
AD25
AD24
T20
AB23
V26
AC24
AB26
Stratix II Development Board
2–25

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