Custom Instruction Tab - Altera Nios II User Manual

Chapter 4: Instantiating the Nios II Processor

Custom Instruction Tab

Debug Signals
The Include debugreq and debugack signals debug signals setting provides the
following functionality. When on, the Nios II processor includes debug request and
acknowledge signals. These signals let another device temporarily suspend the
Nios II processor for debug purposes. The signals are exported to the top level of your
Qsys system.
f
For more information about the debug signals, refer to the
chapter of the Nios II Processor Reference Handbook.
Break Vector
When the Nios II processor contains a JTAG debug module, Qsys determines a break
vector (break address). Break vector memory is always the processor core you are
configuring. Break vector offset is fixed at 0x20. Qsys calculates the physical address
of the break vector from the memory module's base address and the offset.
When the Nios II processor does not contain a JTAG debug module, you can edit the
break vector parameters in the manner described in
page
Advanced Debug Settings
Debug levels 3 and 4 support trace data collection into an on-chip memory buffer. You
can set the on-chip trace buffer size to sizes from 128 to 64K trace frames, using OCI
Onchip Trace. Larger buffer sizes consume more on-chip M4K RAM blocks. Every
M4K RAM block can store up to 128 trace frames.
1
The Nios II MMU does not support the JTAG debug module trace.
Debug level 4 also supports manual 2X clock signal specification. If you want to use a
specific 2X clock signal in your FPGA design, turn off Automatically generate
internal 2x clock signal and drive a 2X clock signal into your system manually.
f
For more information about trace frames, refer to the
the Nios II Processor Reference Handbook.
Custom Instruction Tab
In Qsys, custom instructions are components in your design that you manually
connect to the processor in the Qsys System Contents tab. Existing custom instruction
components are available on the Component Library tab under Custom Instruction
Modules. Thus, the Custom Instruction tab in the Nios II Processor parameter editor
is not used in Qsys.
To create your own custom instruction using the component editor, click New
Component on the File menu in Qsys. After finishing in the component editor, the
new instruction appears on the Component Library tab under Custom Instruction
Modules in Qsys.
February 2014 Altera Corporation
4–3.
Processor Architecture
"General Exception Vector" on
Processor Architecture chapter of
Nios II Processor Reference Handbook
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