Transceiver Channel Datapath Clocking - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Figure 1–27
for REFCLK pins.
Figure 1–27. AC-Coupled Termination Scheme for a Reference Clock
Note to
(1) For more information about the V
Figure 1–28
configured as a HCSL input.
Figure 1–28. Termination Scheme for a Reference Clock When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe
specification.
(2) Select values as recommended by the PCIe clock source vendor.

Transceiver Channel Datapath Clocking

Channel datapath clocking varies with channel configuration options and PCS
configurations. This section describes the clock distribution from the left PLLs for
transceiver channels and the datapath clocking in various supported configurations.
Table 1–7
Table 1–7. PLL Clocks for Transceiver Datapath
CDR clocks
High-speed clock
Low-speed clock
February 2015 Altera Corporation
shows an example of the termination scheme for AC-coupled connections
LVDS, LVPECL, PCML
(1.2 V, 1.5 V, 3.3 V)
0.1 μF
0.1 μF
Figure 1–27:
value, refer to the
ICM
shows an example termination scheme for the REFCLK pin when
PCI Express
(HCSL)
REFCLK
Source
Figure 1–28:
lists the clocks generated by the PLLs for transceiver datapath.
Clock
Receiver CDR unit
Transmitter serializer block in PMA
Transmitter PCS blocks
Receiver PCS blocks when rate match FIFO enabled
V
ICM
50 Ω
= 50 Ω
Z
0
= 50 Ω
Z
0
50 Ω
Cyclone IV Device Datasheet
(2)
Rs
(2)
Rs
50 Ω 50 Ω
Usage
Cyclone IV GX
REFCLK
chapter.
(1)
Cyclone IV GX
+
REFCLK
-
REFCLK
Cyclone IV Device Handbook,
Volume 2
1–29