10/100/1000 Ethernet - Altera Arria V GX Reference Manual

2–30
Table 2–31. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J1)
A30
A35
A36
A39
A40
A43
A44
A47
A48
B11

10/100/1000 Ethernet

Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
10/100/1000 Mbps
Ethernet MAC
Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board
Reference (U20)
23
25
24
28
2
Arria V GX Starter Board
Reference Manual
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Schematic Signal Name
PCIE_TX_CN3
PCIE_TX_CP4
PCIE_TX_CN4
PCIE_TX_CP5
PCIE_TX_CN5
PCIE_TX_CP6
PCIE_TX_CN6
PCIE_TX_CP7
PCIE_TX_CN7
PCIE_WAKEN
The starter board supports 10/100/1000 base-T Ethernet using an external Marvell
88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The
PHY-to-MAC interface employs a RGMII interface to the Arria V GX. The MAC
function must be provided in the FPGA for typical networking applications.
The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25-MHz
reference clock driven from a dedicated oscillator. The PHY interfaces to a Wurth
Elektronik model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
RXD[3:0]
Marvell 88E1111
TXD[3:0]
PHY
Device
RGMII Interface
Table 2–32 lists the Ethernet PHY interface pin assignments.
Schematic Signal Name
ENET_INTN
ENET_MDC
ENET_MDIO
ENET_RESETN
ENET_RX_CLK
Arria V GX
I/O Standard
Pin Number
AC31 1.5-V PCML Transmit bus
W32 1.5-V PCML Transmit bus
W31 1.5-V PCML Transmit bus
U32 1.5-V PCML Transmit bus
U31 1.5-V PCML Transmit bus
R32 1.5-V PCML Transmit bus
R31 1.5-V PCML Transmit bus
N32 1.5-V PCML Transmit bus
N31 1.5-V PCML Transmit bus
E14 2.5-V
Transformer
Arria V GX
I/O Standard
Pin Number
AG11 2.5-V CMOS
AJ11 2.5-V CMOS
AH11 2.5-V CMOS
AL11 2.5-V CMOS
AL4 2.5-V CMOS
Chapter 2: Board Components
Components and Interfaces
Description
Wake signal
CAT 5 UTP:
- 10BASE-T
RJ45
- 100BASE-TX
- 1000BASE-T
Description
Management bus interrupt
Management bus data clock
Management bus data
Device reset
RGMII receive clock
September 2015 Altera Corporation