10/100/1000 Ethernet - Altera Cyclone IV GX Reference Manual

Chapter 2: Board Components
Components and Transceiver Interfaces

10/100/1000 Ethernet

Figure 2–6. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
Table 2–25. Ethernet PHY Pin Assignments, Signal Names and Functions
Board Reference
U9.82
U9.81
U9.77
U9.75
U9.25
U9.24
U9.23
U9.28
Table 2–26. Ethernet PHY Component Reference and Manufacturing Information
Board
Reference
U9
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A Marvell 88E1111 PHY device is used for 10/100/1000 BASE-T Ethernet connection.
The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA.
The MAC function must be provided in the FPGA for typical networking applications
such the Altera Triple Speed Ethernet MegaCore design. The Marvell 88E1111 PHY
uses 2.5-V and 1.2-V power rails and requires a 25-MHz reference clock driven from a
dedicated oscillator. The device interfaces to a Halo Electronics HFJ11-1G02E model
RJ45 with internal magnetics that can be used for driving copper lines with Ethernet
traffic.
By default, the GXB_RX1 and GXB_TX1 channels of the FPGA are connected to the
Ethernet PHY as shown in
Figure 2–6 shows the SGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
10/100/1000 Mbps
Ethernet MAC
SGMII Interface
Table 2–25 lists the Ethernet PHY interface pin assignments.
Description
SGMII TX data
SGMII TX data
SGMII RX data
SGMII RX data
Management bus control
Management bus data
Management bus interrupt
Device reset
Table 2–26 lists the Ethernet PHY interface component reference and manufacturing
information.
Description
Ethernet PHY BASE-T device
Table 2–27 on page 2–22.
Marvell 88E1111
PHY
Device
Schematic Signal Name
ENET_TX_P
ENET_TX_N
ENET_RX_P
ENET_RX_N
ENET_MDC
ENET_MDIO
ENET_INTn
ENET_RESETn
Manufacturer
Marvell Semiconductor 88E1111-B2-CAAIC000
Cyclone IV GX Transceiver Starter Board Reference Manual
RJ45
Cyclone IV GX
Device
I/O Standard Pin Number
1.4-V PCML
2.5-V
Manufacturing Manufacturer
Part Number Website
www.marvell.com
2–21
C2
C1
E2
E1
N9
K8
F12
K9