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OPERATION
this fault is based on an ADC read and can take up to t
to detect. If there is a concern about the input supply
VERT
boosting, keep the part in discontinuous conduction mode.
If the part is set to discontinuous mode operation, as the
inductor average current increases, the controller will
automatically modify the operation from discontinuous
mode to continuous mode.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the PWM can be established
with an internal oscillator or an external time base. The
internal phase-locked loop (PLL) synchronizes the PWM
control to this timing reference with proper phase relation,
whether the clock is provided internally or externally. The
device can also be configured to provide the master clock
to other devices through PMBus command, NVM setting,
or external configuration resistors as outlined in Table 3.
As clock master, the LTM4700 will drive its open-drain
SYNC pin at the selected rate with a pulse width of 500ns.
An external pull-up resistor between SYNC and V
required in this case. Only one device connected to SYNC
should be designated to drive the pin. The LTM4700 will
automatically revert to an external SYNC input, disabling
its own SYNC, as long as the external SYNC frequency is
greater than 80% of the programmed SYNC frequency.
The external SYNC input shall have a duty cycle between
20% and 80%.
Whether configured to drive SYNC or not, the LTM4700 can
continue PWM operation using its own internal oscillator
if an external clock signal is subsequently lost.
The device can also be programmed to always require an
external oscillator for PWM operation by setting bit 4 of
MFR_CONFIG_ALL. The status of the SYNC driver circuit
is indicated by bit 10 of MFR_PADS.
The MFR_PWM_CONFIG command can be used to con-
figure the phase of each channel. Desired phase can also
be set from EEPROM or external configuration resistors
as outlined in Table 3. Designated phase is the relationship
between the falling edge of SYNC and the internal clock
edge that sets the PWM latch to turn on the top power
switch. Additional small propagation delays to the PWM
CON-
control pins will also apply. Both channels must be off
before the FREQUENCY_SWITCH and MFR_PWM_CONFIG
commands can be written to the LTM4700.
The phase relationships and frequency options provide for
numerous application options. Multiple LTM4700 modules
can be synchronized to realize a PolyPhase array. In this
case the phases should be separated by 360/n degrees,
where n is the number of phases driving the output volt-
age rail.
PWM LOOP COMPENSATION
The internal PWM loop compensation resistors R
of the LTM4700 can be adjusted using bit[4:0] of the
MFR_PWM_COMP command.
The transconductance (gm) of the LTM4700 PWM error
amplifier can be adjusted using bit[7:5] of the MFR_PWM_
COMP command. These two loop compensation param-
eters can be programmed when device is in operation.
is
Refer to the Programmable Loop Compensation subsection
DD33
in the Applications Information section for further details.
OUTPUT VOLTAGE SENSING
Both channels in LTM4700 have differential amplifiers,
which allow the remote sensing of the load voltage be-
tween V
OSNSn
also fully differential and makes measurements between
+
V
and V
OSNSn
pins, respectively. The maximum allowed 3.6V, but the
LTM4700 design is limited to 1.8V output.
INTV
AND BUILD-IN 5V BIAS CONVERTER
CC
The internal INTV
pin through a LDO to supply most of the internal circuitry
and the internal top and bottom MOSFET drivers.
The typical INTV
150mA. A 12V input voltage would equate to a difference
of 7V drop across the internal LDO, when multiplied by
150mA equals a 1.05W power loss.
For more information
www.analog.com
LTM4700
+
–
and V
pins. The telemetry ADC is
OSNSn
–
voltages for both channels at the
OSNSn
regulator is powered from the SV
CC
current for the LTM4700 is around
CC
COMPna
IN
Rev. B
27
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