Pwm Outputs; Headphone Outputs - Analog Devices ADAV4622 Manual

ADAV4622
LRCLK
BCLK
MSB
SDO0
LRCLK
BCLK
MSB
SDO0
LRCLK
BCLK
SDO0

PWM OUTPUTS

In the ADAV4622, the main outputs are available as four PWM
output channels, which are suitable for driving Class-D amplifiers.
PWM_Ready is a status pin used to signify that the ADAV4622
PWM outputs are in a valid state. During PWM power-up and
power-down, this pin remains low to signify that the outputs
are not in a valid state. The output power stage should remain
muted until this pin goes high. This functionality helps to
eliminate pop/click and other unwanted noise on the outputs.
PWM
MODULATOR
PWM
MODULATOR
PWM
MODULATOR
PWM
MODULATOR
Figure 29. PWM Output Section
Each set of PWM outputs is a complementary output. The
modulation frequency is 384 kHz, and the full-scale duty cycle
has a ratio of 97:3.
Full details on the use of the PWM outputs are available upon
request. Contact a local Analog Devices sales representative for
more details.
LEFT CHANNEL
LSB
LEFT CHANNEL
LSB
Figure 27. Left-Justified Mode
LEFT CHANNEL
MSB
Figure 28. Right-Justified Mode
+
PWM1A
–
PWM1B
+
PWM2A
–
PWM2B
+
PWM3A
–
PWM3B
+
PWM4A
–
PWM4B
PWM_READY
MSB
1 /F
S
2
Figure 26. I S Mode
MSB
1 /F
S
LSB
1 /F
S

HEADPHONE OUTPUTS

There are two stereo headphone amplifier outputs capable
of driving 32 Ω loads at 1 V rms. HPOUT1 is shared with
AUXOUT4, and HPOUT2 is shared with AUXOUT2, as shown
in Figure 30.
2
I S DIGITAL AUDIO OUTPUTS
2
One I S output, SDO0, uses the same serial clocks as the serial
inputs, which are BCLK1 and LRCLK1 by default. If an addi-
tional digital output is required, an additional pin can be
reconfigured as a serial digital output, as shown in Figure 31.
L
R
L
R
Rev. B | Page 24 of 28
RIGHT CHANNEL
LSB
RIGHT CHANNEL
LSB
RIGHT CHANNEL
MSB
AUXOUT4L
PA
HPOUT1L
HPOUT1R
DAC
AUXOUT4R
AUXOUT2L
PA
HPOUT2L
HPOUT2R
DAC
AUXOUT2R
Figure 30. Headphone Outputs Section
2
I S OUTPUT
INTERFACE
S/PDIF
OUTPUT
BCLK1
LRCLK1
2
Figure 31. I S Digital Outputs
LSB
SDO0
SPDIF_OUT (SDO1)