Synchronization Controller - Analog Devices AD9739 Manual

SYNCHRONIZATION CONTROLLER

A top level diagram of the synchronization circuitry and
controller is shown in Figure 92. The synchronization circuitry
requires a sync signal into the DAC (SYNC_IN_x) to set the
clock divider. The frequency of the SYNC_IN_x signal must be
1/4 the DACCLK_x frequency (that is, for DACCLK_x = 2.5
GSPS, the SYNC_IN_x signal must be 625 MSPS). The
SYNC_IN_x signal can be provided externally; however, it is
recommended to use the SYNC_OUT_x signal provided by the
master DAC through a fanout chip to all DACs in the system
(including the master). Using the SYNC_OUT_x signal from
the DAC allows for continuous adjustment over temperature for
SYNC_IN_x
SYNC_OUT_x
FF
FF
SYNC_DEL
FF
C1_DEL
C0_DEL
FF
FF
0
1
3
DELAY
SYNC_TRACK
DELAY
Figure 92. Top Level Block Diagram of Synchronization Circuitry and Controller
Rev. A | Page 43 of 56
proper SYNC_IN_x position. The synchronization circuitry has
two modes of operation, master and slave. In master mode, the
sync operation starts an initialization phase that determines the
proper position of the SYNC _IN_x signal by adjusting the
SYNC_ OUT_x delay line. When the SYNC_IN_x position is
locked, the master selects the correct SYNC_OUT_x phase
(and, consequently, SYNC_IN_x). After SYNC_IN_x is placed
in the center of the sampling window, and the appropriate phase
is selected, the clock divider phase is adjusted, and the master
controller enters tracking mode to maintain the SYNC_IN_x
position across temperature.
DCI WINDOW SAMPLE
DCI WINDOW POST
DCI WINDOW PRE
CONTROLLER
SO DELAY SO SELECT
0
2
DELAY
1
3
SYNC_OUT
DELAY
PHASE
0
DAC
2
/4
CLOCK
1
3
AD9739