Dma Transfer Control Block Registers - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Transfer Control Block Registers

The registers used to control and configure DMA operations are part
TCB
of the memory-mapped register sets ("DMA Registers" on page 2-41).
These can be accessed as quad-words only.
The remaining sections in this chapter describe the different operating
modes of the DMA controller together with the associated control regis-
ters and bits. DMA
DMA Channel Control
Each of the four external memory DMA channels is controlled by a
quad-word register pair. In addition, each of the four link ports to or from
memory DMA channels is controlled by a
each of the two AutoDMA registers-to-memory DMA channels is con-
trolled by a
TCB
Transfer Control Block (TCB) Registers
Each register is 128 bits long and is divided into four 32-bit registers
TCB
These registers are illustrated in Figure 7-4.
• Index register (
• X dimension count and increment register (
• Y dimension count and increment register (
• Control and chaining pointer (
ADSP-TS101 TigerSHARC Processor
Hardware Reference
registers are detailed in the following subsections.
TCB
quad-word register.
)
DI
Direct Memory Access
quad-word register. Finally,
TCB
)
DX
)
DY
)
DP
TCB
7-15