Dma Transfers; Core Driven Transfers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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Using the Parallel Port

over core driven transfers is that the core can continue executing code

while sequential data is imported/exported in the background.

Unlike the external port on previous SHARC processors, the ADSP-2126x

core cannot directly access the external parallel bus. Instead, the core ini-

tializes two registers to indicate the external address and address-modifier

and then accesses data through intermediate registers. Then, when the

core accesses either the

writes/fetches data to/from the specified external address. The details of

this functionality and the four main techniques to manage each transfer

are detailed below. In general, core-driven transfers are most advantageous

when performing single-word accesses and/or accesses to non-sequential

DMA Transfers

To use the parallel port for DMA programs, start by setting up values in

the DMA parameter registers. The program then writes to the

ter to enable

value, transfer direction, and so on. While a parallel port DMA is active,

the DMA parameter registers are not writable. Furthermore, only the

bits (in the

changed, the parallel port will malfunction. It is recommended that both

To see an example program that sets up a parallel port DMA, see

Listing 8-1 on page

Core-driven transfers can be managed using four techniques. The transfers

can 1) use interrupts, 2) poll status bits in the

when each access will complete by calculating the data and

tions, or 4) rely on the fact that the core stalls on certain accesses to

with all of the necessary settings like cycle duration

bits be set and reset together to ensure proper DMA

ADSP-2126x SHARC Processor Hardware Reference

registers, the parallel port