Setting Up Dma Transfers - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Setting Up DMA Transfers

The process in which the TigerSHARC processor's DMA control-
ler downloads a
register.
• AutoDMA registers
Two virtual DMA registers that can only be accessed by a cluster
bus master. These registers allow data to be moved to a block
defined by the channel's
"AutoDMA Register Control" on page 7-33.
Setting Up DMA Transfers
DMA operations can be programmed by the TigerSHARC processor core
processor, by an external host processor, or by the (external) TigerSHARC
processor bus master. The operation is programmed by writing to the
memory-mapped DMA
ister that indicates the DMA block transfer. A DMA channel is set up by
writing a quad-word to each of the DMA
be loaded with a starting address for the block, an address modifier, and a
word count. Similar to link DMA channels, an AutoDMA register chan-
nel has only one
In the case of link ports, once a DMA block is set up and enabled, data
words received are automatically transferred to the internal memory or
external memory or to another link port transmit buffer. Likewise, when
the transmitting link is ready to transmit data, a quad-word is automati-
cally transferred from internal or external memory to the transmitter link
buffer. These transfers continue until the entire data buffer is received or
transmitted.
If the is programmed to issue an interrupt, then DMA interrupts are
TCB
generated when an entire block of data has been transferred. This occurs
when the DMA channel's count register has decremented to zero and the
last element of data has been transferred.
7-14
from memory and autoinitializes the DMA
TCB
TCB
registers. The
TCB
register.
TCB
register. For more information, see
register is a quad-word reg-
TCB
registers. Each register must
TCB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
TCB