Ddr2 Sdram - Analog Devices ADSP-BF609 EZ-KIT Lite Manual

DDR2 SDRAM

The board has a 16M x 16-bit burst flash memory connected to the pro-
cessor's Static Memory Controller (SMC). The processor also is connected
to a 32 Mb quad serial flash memory via the Serial Peripheral Interface
(SPI). Both flash memories can be used for non-volatile data storage and
processor boot.
DDR2 SDRAM
The ADSP-BF609 processor connects to a 128 MB Micron
MT47H64M16HR-3 chip through the Double Data Rate Synchronous
Dynamic Random-Access Memory (DDR2 SDRAM) controller. The
DDR2 memory controller on the processor and DDR2 memory chip are
powered by the on-board 1.8V regulator. Data is transferred between the
processor and DDR2 on both the rising and falling edges of the DDR2
clock. The DDR2 controller on the processor can operate at a maximum
clock frequency of 250 MHz.
With a CCES session running and connected to the EZ-KIT Lite via the
USB standalone debug agent, the DDR2 registers are configured automat-
ically each time the processor is reset. The values are used whenever
DDR2 is accessed through the debugger (for example, when viewing
memory or loading a program).
To disable the automatic setting of the DDR2 registers, select Target >
Settings > Target Options in CCES and disable Use XML reset values.
An example program is included in the EZ-KIT Lite installation directory
to demonstrate how to setup and access the DDR2 interface. For more
information on how to initialize the registers after a reset, refer to the
hardware reference manual.
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