Sdrcon (Sdram Configuration) (Dma 0X180484) - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Register Access Features

SDRCON (SDRAM Configuration) (DMA 0x180484)

The register defines SDRAM configuration. The
SDRCON
can be written only once after reset and cannot be changed during system
operation. The initial value of the
ing that the SDRAM is disabled.
Figure 2-12. SDRCON (Upper) Register Bit Descriptions
The bit descriptions for this register are shown in Figure 2-12 on
page 2-36 and Figure 2-13 on page 2-37.
2-36
register after reset is zero, mean-
SDRCON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved Bit15 continued on Figure 2-13
ADSP-TS101 TigerSHARC Processor
register
SDRCON
Hardware Reference