Program Memory Interface; External Program Memory Read/Write - Analog Devices adsp-2100 Manual

10.2

PROGRAM MEMORY INTERFACE

This section describes the program memory interface of all ADSP-21xx
processors except the ADSP-2181.
The processors address 16K of 24-bit wide program memory, up to 2K
on-chip and the remainder external, using the control lines shown in
Figure 10.1. The processors supply a 14-bit address on the program
memory address bus (PMA) which is driven off-chip on the address bus in
the case of external program memory accesses. Instructions or data are
transferred across the 24-bit program memory data (PMD) bus which is
also multiplexed off-chip. For a dual off-chip data fetch, the data from
program memory is read first, then the data memory data. A program
memory select pin,
with a program memory address and memory can be selected.
Two control lines indicate the direction of the transfer. Memory read (
is active low signaling a read and memory write (
write operation. Typically, you would connect
to (Output Enable) and
RD OE
10.2.1 External Program Memory Read / Write
On-chip memory accesses do not drive any external signals.
RD WR
, and remain high (deasserted); the address and data buses are
tristated. Off-chip program memory access happens in this sequence:
1. The processor places the address on the PMA bus, which is
multiplexed off-chip, and
RD WR
2. or is asserted.
3. Within a specified time, data is placed on the data bus, multiplexed to
the internal PMD bus.
4. The data is read or written and
PMS
5. is deasserted.
The basic read and write cycles are illustrated in Figure 10.2 on the next
page. Figure 10.2A shows zero wait states and 10.2B shows the effect of
one wait state.
Memory Interface
, indicates that the address bus is being driven
PMS
to
WR WE
PMS
is asserted.
RD
) is active low for a
WR
to
PMS CE
(Write Enable) of your memory.
WR
(or ) is deasserted.
)
RD
(Chip Enable),
PMS DMS
, ,
10
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