Fsk Demodulator Optimization - Analog Devices ADF7021-V Manual

3FSK CDR Setup
In 3FSK, a transmit preamble of at least 40 bits of continuous
1s is recommended to ensure a maximum number of symbol
transitions for the CDR to acquire lock.
The clock and data recovery for 3FSK requires a number of
parameters in Register 13 to be set (see Table 19).
4FSK Threshold Detector Setup
The threshold for the 4FSK detector is set using the
3FSK/4FSK_SLICER_THRESHOLD bits (Register 13,
Bits[DB10:DB4]). The threshold should be set as follows:
3FSK/4FSK_SLICER_THRESHOLD =
⎛
4FSK Outer Tx Deviation
⎜
×
78
⎜
×
100
⎝
where K is the value calculated for correlator discriminator
bandwidth.

FSK DEMODULATOR OPTIMIZATION

2FSK Preamble
The recommended preamble bit pattern for 2FSK, GFSK, and
RC2FSK is a dc-free pattern (such as a 10101010... pattern).
Preamble patterns with longer run-length constraints (such as
Table 19. 3FSK CDR Settings
Parameter (Register 13)
PHASE_CORRECTION (Bit DB12)
3FSK_CDR_THRESHOLD (Bits[DB21:DB15])
3FSK_PREAMBLE_TIME_VALIDATE (Bits[DB25:DB22])
Table 20. Preamble Bit Length for 2FSK Modulation
Demodulator
Correlator (AFC off )
Mod index = 2
Mod index = 1
Mod index = 0.5
Linear (AFC off )
f = 4.2 kHz
DEV
f = 2.2 kHz
DEV
f = 1.6 kHz
DEV
Correlator (AFC on)
Linear (AFC on)
Correlator + bypass CDR (AFC off )
1 This value is generally true; however, some sensitivity degradation may occur close to the edge of the IF filter.
2
Limited to ±0.5 × IFBW or AFC pull-in range, whichever is less.
3
Dependent on modulation index and f
minimum preamble length increases as the modulation index and f
4 Dependent on the performance of the symbol timing recovery module on the external microcontroller.
5
Depends on the pulse width mark/space ratio of Logic 1 to Logic 0 that the symbol timing recovery scheme on the external microcontroller can tolerate. In this mode,
the mark/space ratio of the recovered bit stream increases with frequency error. In the absence of frequency error, the mark/space ratio is 50:50, that is, the width of a
Logic 1 is the same as the width of a Logic 0.
⎞
×
K
⎟
⎟
3
10
⎠
Recommended Setting
1
62
where K is the value calculated for correlator
discriminator bandwidth.
15
Sensitivity Degradation
from Specifications
0 dB
0 dB
0 dB
3 dB
3 dB
3 dB
2 dB
3 dB
2 dB to 3 dB 4
. At higher modulation indexes (1.0 or greater) and higher f
DEV
DEV
11001100...) can also be used, but result in a longer synchro-
nization time of the received bit stream in the receiver. The
preamble must allow enough bits for AGC settling of the
receiver and CDR acquisition (see Table 20).
The remaining fields that follow the preamble do not need to
use dc-free coding. For these fields, the ADF7021-V can accom-
modate coding schemes with a run length of greater than eight
bits without any performance degradation. Refer to the AN-915
Application Note for more information.
4FSK Preamble and Data Coding
The recommended preamble bit pattern for 4FSK is a repeating
00100010... bit sequence. This two-level sequence of repeating
−3, +3, −3, +3 symbols is dc-free and maximizes the symbol
timing performance and data recovery of the 4FSK preamble
in the receiver. The minimum recommended length of the
preamble is 32 bits (16 symbols).
The remainder of the 4FSK packet should be constructed so
that the transmitted symbols retain close to a dc-free balance by
using data scrambling and/or by inserting specific dc-balancing
symbols in the transmitted bit stream at regular intervals, such
as after every 8 or 16 symbols.
⎛
Tx _ FREQUENCY _ DEVIATION
⎜
×
⎜
×
3
100 10
⎝
Rx Frequency Error
Tolerance (1% PER)
±30% × f
DEV
±25% × f
DEV
±20% × f
DEV
1
±0.5 × IFBW
1
±0.5 × IFBW
1
±0.5 × IFBW
AFC pull-in range
AFC pull-in range
±50% × f 5
DEV
(>4.0 kHz), the minimum preamble length is 96 bits. The
DEV
are reduced.
Rev. 0 | Page 33 of 60
Purpose
Phase correction is on
⎞ Sets CDR decision threshold levels
×
K
⎟
⎟
⎠
Preamble detector time qualifier
Minimum Preamble (Bits)
16
16
16
64
112
128
2 3
96 to 128
2
96 to 128
8
ADF7021-V