Polyphase Load Sharing; Internal Temperature Sense; Rconfig (Resistor Configuration) Pins - Analog Devices LTM4683 Manual

LTM4683
OPERATION

PolyPhase LOAD SHARING

Multiple LTM4683s can be arrayed to provide a balanced
load-share solution by bussing the necessary pins.
Figure 50 illustrates an 8-phase design sharing connec-
tion required for load sharing.
If an external oscillator is not provided, the SYNC_nn pins
should only be enabled on one of the LTM4683s con-
trollers. The other(s) should be programmed to disable
SYNC_nn controllers using bit 4 of MFR_CONFIG_ALL. If
an external oscillator is present, the chip with the SYNC nn
pin enabled will detect the presence of the external clock
and disable its output.
Multiple channels need to tie all the V
–
and all the V pins together, C
OSNSn
together as well. Do not assert bit[4] of MFR_CONFIG_ ALL
except in a PolyPhase application.
®
The user must share the SYNC_nn, SHARE_CLK_nn,
FAULTn, and ALERTn pins of these parts. Use pull-up
resistors on SYNC_nn, FAULTn, SHARE_CLK_nn, and
ALERTn. See the Typical Applications figures.

INTERNAL TEMPERATURE SENSE

Temperature is measured using the internal diode-con-
nected PNP transistors, and the outputs are connected to
TSNS0 to TSNS3 pins corresponding to Channels 0 to 3.
These outputs are used for testing. Two different currents
are applied to the diode (nominally 2µA and 32µA), and
the temperature is calculated from a ∆V
made with the internal 16-bit monitor ADC (see Figure 2
Simplified Block Diagram).
The LTM4683 will only implement ∆V
sensing; therefore MFR_PWM_MODE bit [5] is reserved.
R (RESISTOR CONFIGURATION) PINS
CONFIG
There are twelve input pins utilizing 1% resistors between
these pins to select key operating parameters. The pins
are ASEL_01, ASEL_23, FSWPH_01_CFG, FSWPH_23_
CFG, VOUT0_CFG, VOUT1_CFG, VOUT2_CFG, VOUT3_
CFG, VTRIM0_CFG, VTRIM1_CFG, VTRIM2_CFG, and
VTRIM3_CFG. If pins are floated, the value stored in the
34
+
pins together,
OSNSn
and C pins
OMPna OMPnb
measurement
BE
temperature
BE
For more information
corresponding NVM command is used. If bit 6 of the
MFR_CONFIG_ALL configuration command is asserted in
NVM, the resistor input is ignored upon power-up except
for ASEL, which is always respected. The resistor con-
figuration pins are only measured during a power-up reset
or, after a MFR_RESET, or after a RESTORE_USER_ALL
command is executed.
The VOUTn_CFG pin settings are described in Table 1.
These pins set the LTM4683 V
coarse settings. If the pin is open, the VOUT_COMMAND
command is loaded from NVM to determine the output
voltage. The default setting is to have the switcher off
unless the voltage configuration pins are installed. The
VTRIMn_CFG pins in Table 2 are used to set the output
voltage fine adjustment setting. Both combine to offer
several distinct output voltages.
The following parameters are set as a percentage of the
output voltage if the R
CONFIG
the output voltage.
VOUT_OV_FAULT_LIMIT ....................................+10%
n
VOUT_OV_WARN_LIMIT ....................................+7.5%
n
VOUT_MAX .........................................................+7.5%
n
VOUT_MARGIN_HIGH ........................................+5%
n
VOUT_MARGIN_LOW .........................................–5%
n
VOUT_UV_FAULT_LIMIT ....................................–7%
n
The FSWPH_CFG_nn pin settings are described in Table 3.
This pin selects the switching frequency and phase of each
channel. The phase relationships between the two chan-
nels and the SYNC_nn pin are determined in Table 3. To
synchronize to an external clock, the part should be put into
external clock mode (SYNC_nn output disabled, but fre-
quency set to the nominal value). If no external clock is sup-
plied, the part will clock at the programmed frequency. If the
application is multiphase and the SYNC_nn signal between
chips is lost, the parts will not operate at the designed
phase, even if they are programmed and trimmed to the
same frequency. This can increase the ripple voltage on
the output, possibly producing undesirable operation. If
the external SYNC_nn signal is being generated internally
and external SYNC_nn is not selected, bit 10 of MFR_
PADS will be asserted. If no frequency is selected and the
external SYNC_nn frequency is not present, a PLL_FAULT
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to V output voltage
OUT0 OUT3
pins are used to determine
Rev. 0