Internal Memory Access - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Table 2-4. Internal Address Space
Bits
ADDR18–0
ADDR21–19
ADDR31–22
Access to Uregs (ISPACE = 011) is only for multiprocessing space. Inter-
nal access to registers cannot be memory mapped—in load/store
instructions, for example, the address cannot point to a register through
the internal space. The DMA also cannot access a register directly,
although there is an exception—link receive DMA channels may write to
other link transmit registers.

Internal Memory Access

In addition to the direct accesses (normal - one 32-bit word, long - two
32-bit words, and quad - four 32-bit words), several other efficient meth-
ods are available. These include Broadcast Write, Merged Distribution,
and Broadcast Distribution. Broadcast Write is an external write to other
DSPs in a multiprocessor cluster. Merged and Broadcast Distribution are
internal access methods. For additional information on memory access
methods, see "IALU" in the ADSP-TS101 TigerSHARC Processor Program-
ming Reference. "Merged Access" on page 2-11 also provides additional
information regarding these access modes.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Name or Value Definition
Address Address
ISPACE Internal Space—determines the internal space.
000 – Block 0
001 – Block 1
010 – Block 2
011 – Internal Registers (Uregs)
1XX – Reserved
PRID Internal space if 000 00
Memory and Register Map
2-7